Photo News
- 2025.11.07
- 15
Jaegeun Lim, Integrated M.S.–Ph.D. (Advisor: Prof. Gilcho Ahn),
Paper Accepted to JSSC 2025
▲ (From left) Professor Gilcho Ahn, integrated M.S.–Ph.D. student Jaegeun Lim
Jaegeun Lim, an integrated M.S.–Ph.D. student in the Mixed-Signal Circuit Design Lab (advisor: Gilcho Ahn) in our Department of Electronic Engineering, has had a paper accepted to the IEEE Journal of Solid-State Circuits (JSSC), the most prestigious international journal in analog circuit design (JCR Impact Factor 5.6, 2025).
The IEEE Journal of Solid-State Circuits (JSSC) is a monthly journal that publishes across a broad range of semiconductor circuit topics with a particular emphasis on transistor-level integrated-circuit design. It also covers subjects directly related to IC design such as circuit modeling, technology, system design, layout, and test.
The accepted paper, titled “A Hybrid Voltage-Time Domain Pipelined ADC With Reference-Embedded Time-Domain Residues,” proposes an 12-bit ADC that uses dual residues to inherently compensate time-domain reference variation without off-chip trimming or background calibration, thereby ensuring full-scale reference matching across the hybrid-domain stages.