서강대학교 전자공학과

Winner of the Excellent Design and Excellent Poster Awards

at the 27th Korean Conference on Semiconductors

Professor Choi Woo Young's research team won the Excellent Design Award and the Excellent Poster Award at the 27th Korean Conference on Semiconductors (KCS) held in Gangwon-do in February. This conference, which is a major academic conference in the field of semiconductors, was arranged to discuss semiconductor technology innovation that will lead the next generation of major ICT convergence technologies and directions for the future.

Kwon Hyug Su, who received the excellent design award, is in doctoral program in the Department of Electronic Engineering (Advisor: Prof. Choi Woo Young). He was the first in the world to experimentally implement the single tile operation of CMOS-NEM reconfigurable logic device/circuit using a nanoelectromechanical (NEM) device.

The CMOS-NEM reconfigurable logic device/circuit presented through this study was implemented based on 65 nm process technology, and the NEM device responsible for signal change was implemented in the post-process wiring section. This device/circuit is expected to have a chip density 4.6 times higher, an operating frequency 2.3 times higher, and a power consumption 9.3 times lower than a conventional CMOS device-only circuit. With higher speed and lower power consumption equivalent to the ASIC (Application Specific Integrated Circuit) level, it is also expected to make a great contribution to implementing a field-programmable gate array (FPGA) with microprocessor-level operational flexibility.

This technology, implemented for the first time in the world, has the characteristics of a source technology that can change the paradigm of semiconductor technology, not just the field of reconfigurable logic device/circuit technology. In the short term, it is possible to expand into the field of ultra-low-power memory-in-logic and analog computing, and ultimately, it is expected to enable the emergence of ultra-low-power three-dimensional neuro-simulation semiconductor chips.

▶Thesis Title: Monolithic three-dimensional (M3D) CMOS- Nanoelectromechanical (NEM) Single-tile Reconfigurable Logic (RL)

▶Authors: Kwon Hyug Su (First author), Ph.D. candidate, and Professor Choi Woo Young (Second author)

In the same competition, Kang Min Hee, a master's student in Electronic Engineering (Advisor: Prof. Choi Woo Young) was awarded the Outstanding Poster Award in recognition of its contribution to improving the reliability of NEM by alleviating the stress of NEM through selection line optimization.

The NEM of the selection line optimization structure presented this time was verified for its efficacy through the finite element method, and showed that the stress concentrated on the anchor part of the NEM was reduced as the selection line was reduced. In addition, the optimal selection line length was demonstrated, showing the change in NEM pull-in voltage that occurs while reducing the selection line. The NEM of the selection line optimization proposed by the research team is expected to reduce stress by over 40% compared to the existing structure. Through this, it is expected that the proposed structure will greatly contribute to improving the reliability of CMOS-NEM hybrid circuits.

▶Thesis Title: Selection Line Optimization of Nanoelectromechanical (NEM) Memory Switches for Stress Relief

▶Authors: Kang Min Hee, Master's candidate (First author), Professor Choi Woo Young (second author)